Search results for "Network on"
showing 10 items of 38 documents
Multi-application Based Fault-Tolerant Network-on-Chip Design for Mesh Topology Using Reconfigurable Architecture
2019
In this paper, we propose a two-step fault-tolerant approach to address the faults occurred in cores. In the first stage, a Particle Swarm Optimization (PSO) based approach has been proposed for the fault-tolerant mapping of multiple applications on to the mesh based reconfigurable architecture by introducing spare cores and a heuristic has been proposed for the reconfiguration in the second stage. The proposed approach has been experimented by taking several benchmark applications into consideration. Communication cost comparisons have been carried out by taking the failed cores as user input and the experimental results show that our approach could get improvements in terms of communicati…
Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing
2010
The high-performance computing domain is enriching with the inclusion of Networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while meeting tight power, area and latency constraints. Designers must address new challenges that were not present before. Defective components, the enhancement of application-level parallelism or power-aware techniques may break topology regularity, thus, efficient routing becomes a challenge.In this paper, uLBDR (Universal Logic-Based Distributed Routing) is proposed as an efficient logic-based mechanism that adapts to any irregular topology derived from 2D meshes, being an alter…
Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology
2010
Nowadays, system designers have adopted Networks-on-Chip as communication infrastructure of general-purpose tile-based Multi-Processor System-on-Chip (MPSoC). Such decision implies that a certain topology has to be selected to efficiently interconnect many cores on the chip. To ease such a choice, the networking literature offers a plethora of works about topology analysis and characterization for the off-chip domain. However, theoretical parameters and many intuitive assumptions of such off-chip networks do not necessarily hold when a topology is laid out on a 2D silicon surface. This is due to the distinctive features of silicon technology design pitfalls. This work is a first milestone t…
Comparison of different methods to assess the distribution of alien plants along the road network and use of Google Street View panoramas interpretat…
2021
The survey by foot in the field is compared to the survey from a car, the photo-interpretation of Google Street View (GSV) panoramas continuously and at intervals of 1.5 km and the photo-interpretation of Google Earth aerial images on a 10 km stretch of road in Sicily. The survey by foot was used as reference for the other methods. The interpretation of continuous GSV panoramas gave similar results as the assessment by car in terms of the number of species identified and their location, but with lower cost. The interpretation online of aerial photos allowed the identification of a limited number of taxa, but gave a good localisation for them. Interpretation of GSV panoramas, each of 1.5 km,…
Multi-application Based Network-on-Chip Design for Mesh-of-Tree Topology Using Global Mapping and Reconfigurable Architecture
2019
This paper outlines a multi-application mapping for Mesh-of-Tree (MoT) topology based Network-on-Chip (NoC) design using reconfigurable architecture. A two phase Particle Swarm Optimization (PSO) has been proposed for reconfigurable architecture to minimize the communication cost. In first phase global mapping is done by combining multiple applications and in second phase, reconfiguration is achieved by switching the cores to near by routers using multiplexers. Experimentations have been carried out for several application benchmarks and synthetic applications generated using TGFF tool. The results show significant improvement in terms of communication cost after reconfiguration.
Torus Topology based Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement
2018
The increase in the density of the IP cores being fabricated on a chip poses on-chip communication challenges and heat dissipation. To overcome these issues, Network-onChip (NoC) based communication architecture is introduced. In the nanoscale era NoCs are prone to faults which results in performance degradation and un-reliability. Hence efficient fault-tolerant methods are required to make the system reliable in contrast to diverse component failures. This paper presents a flexible spare core placement in torus topology based faulttolerant NoC design. The communications related to the failed core is taken care by selecting the best position for a spare core in the torus network. By conside…
A common SNP in the UNG gene decreases ovarian cancer risk in BRCA2 mutation carriers
2018
Single nucleotide polymorphisms (SNPs) in DNA glycosylase genes involved in the base excision repair (BER) pathway can modify breast and ovarian cancer risk in BRCA1 and BRCA2 mutation carriers. We previously found that SNP rs34259 in the uracil-DNA glycosylase gene (UNG) might decrease ovarian cancer risk in BRCA2 mutation carriers. In the present study, we validated this finding in a larger series of familial breast and ovarian cancer patients to gain insights into how this UNG variant exerts its protective effect. We found that rs34259 is associated with significant UNG downregulation and with lower levels of DNA damage at telomeres. In addition, we found that this SNP is associated with…
Recommendations for the introduction of metagenomic high-throughput sequencing in clinical virology, part I: Wet lab procedure
2020
Metagenomic high-throughput sequencing (mHTS) is a hypothesis-free, universal pathogen detection technique for determination of the DNA/RNA sequences in a variety of sample types and infectious syndromes. mHTS is still in its early stages of translating into clinical application. To support the development, implementation and standardization of mHTS procedures for virus diagnostics, the European Society for Clinical Virology (ESCV) Network on Next-Generation Sequencing (ENNGS) has been established. The aim of ENNGS is to bring together professionals involved in mHTS for viral diagnostics to share methodologies and experiences, and to develop application recommendations. This manuscript aims…
An efficient distributed algorithm for generating and updating multicast trees
2006
As group applications are becoming widespread, efficient network utilization becomes a growing concern. Multicast transmission represents a necessary lower network service for the wide diffusion of new multimedia network applications. Multicast transmission may use network resources more efficiently than multiple point-to-point messages; however, creating optimal multicast trees (Steiner Tree Problem in networks) is prohibitively expensive. This paper proposes a distributed algorithm for the heuristic solution of the Steiner Tree Problem, allowing the construction of effective distribution trees using a coordination protocol among the network nodes. Furthermore, we propose a novel distribut…
Domain-Knowledge Optimized Simulated Annealing for Network-on-Chip Application Mapping
2013
Network-on-Chip architectures are scalable on-chip interconnection networks. They replace the inefficient shared buses and are suitable for multicore and manycore systems. This paper presents an Optimized Simulated Annealing (OSA) algorithm for the Network-on-Chip application mapping problem. With OSA, the cores are implicitly and dynamically clustered using knowledge about communication demands. We show that OSA is a more feasible Simulated Annealing approach to NoC application mapping by comparing it with a general Simulated Annealing algorithm and a Branch and Bound algorithm, too. Using real applications we show that OSA is significantly faster than a general Simulated Annealing, withou…